Enhanced back-channel leakage in a mesa SOI device architecture is analyzed
. Using integrated process, device, and hole trapping simulation, the cause
of the leakage enhancement is identified as enhanced hole trapping in the
buried oxide near the island edge. Simulation results suggest this edge eff
ect may be mitigated using body-tied-to-source tabs at the edge of the isla
nd. The potential performance and manufacturing impacts of this measure are
discussed.