Layout driven selection and chaining of partial scan flip-flops

In an era of sub-micron technology, routing is becoming a dominant factor i n area, timing, and power consumption. In this paper, we study the problem of selection and chaining of scan flip-flops with the objective of achievin g minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan hip-flops as possible to break all cy cles in S-graph. However, the flip-flops that break more cycles are often t he ones that have more fanins and fanouts. The area adjacent to these nodes is often crowded in layout. Such selections will cause layout congestion a nd increase the number of tracks to chain the scan flip-flops. To take layo ut information into consideration, we propose a matching-based algorithm to solve the problem. First, an initial placement will be performed before sc an hip-flops are selected. Then, iteratively, a matching-based algorithm ta king the current layout into account is proposed to select and chain the sc an hip-flops. Experimental results show that, on the average, our algorithm can reduce 8.1% area overhead as compared with the previously proposed met hods that do not utilize the layout information in flip-flop selection.