Cell placement is an important phase of current VLSI circuit design styles
such as standard cell, gate array, and Field Programmable Gate Array (FPGA)
. Although nondeterministic algorithms such as Simulated Annealing (SA) wer
e successful in solving this problem, they are known to be slow. In this pa
per, a neural network algorithm is proposed that produces solutions as good
as SA in substantially less time. This algorithm is based on Mean Field An
nealing (MFA) technique, which was successfully applied to various combinat
orial optimization problems. A MFA formulation for the cell placement probl
em is derived which can easily be applied to all VLSI design styles. To dem
onstrate that the proposed algorithm is applicable in practice, a detailed
formulation for the FPGA design style is derived, and the layouts of severa
l benchmark circuits are generated. The performance of the proposed cell pl
acement algorithm is evaluated in comparison with commercial automated circ
uit design software Xilinx Automatic Place and Route (APR) which uses SA te
chnique. Performance evaluation is conducted using ACM/SIGDA Design Automat
ion benchmark circuits. Experimental results indicate that the proposed MFA
algorithm produces comparable results with APR. However, MFA is almost 20
times faster than APR on the average. (C) 1998 Elsevier Science Ltd. All ri
ghts reserved.