A cost-effective architecture for HDTV video decoder in ATSC receivers

In this paper, we describe the architecture of an HDTV video decoder, Vince nt5, for MPEG2 MP@HL video decoding and format conversion of all 18 ATSC DT V formats in real-time. Vincent5 adopts a dataflow architecture for its mai n decoding functions in contrast to the conventional decoders that use a st rict pipelined structure for them. Consequently this makes it possible for us to explore wide design choices in the architecture decision for each dec oding function. In Vincent5 we introduce a new memory control scheme of red ucing the memory bandwidth, which is necessary in MPEG2 MP@HL decoding for a cost-effective solution. Without increasing the hardware complexity of Vi ncent5, we embed three programmable cores into the dedicated hardware to ma ximize its programmability. Vincent5 was described using the VHDL and its f unctionality was verified with standard MPEG2 bitstreams. Vincent5 includes 115K logic gates, 118Kb RAM, and 32Kb ROM after logic synthesis and had be en fabricated utilizing 3ML 0.5um CMOS technology.