The effect of gate recess profile on device performance of Ga0.51In0.49P/In0.2Ga(0.8)As doped-channel FET's

Citation
Ss. Lu et al., The effect of gate recess profile on device performance of Ga0.51In0.49P/In0.2Ga(0.8)As doped-channel FET's, IEEE DEVICE, 46(1), 1999, pp. 48-54
Citations number
18
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
46
Issue
1
Year of publication
1999
Pages
48 - 54
Database
ISI
SICI code
0018-9383(199901)46:1<48:TEOGRP>2.0.ZU;2-B
Abstract
The effect of gate recess profile on device performance of Ga0.51In0.49P/In 0.2Ga0.8As doped-channel FET's was studied, In the experiment, Ga0.51In0.49 P/In0.2Ga0.8As doped-channel FET's (DCFET's) using triple-recessed gate str ucture were compared with devices using single-recessed and double-recessed gate structures, It is found that triple-recessed gate approach provides h igher breakdown voltage (35 V) than single-recessed (16 V) and double-reces sed gate (28 V) approaches, This is attributed to the larger aspect ratio i n the triple-recessed gate structure. A unified method to calculate the bre akdown voltages of MESFET's, HEMT's and DCFET's (or MISFET's) of any given arbitrary recessed gate profile was proposed and used to explain the experi mental results.