A VLSI architecture design for dual-mode QAM and VSB digital CATV transceiver

Citation
Mt. Shiue et al., A VLSI architecture design for dual-mode QAM and VSB digital CATV transceiver, IEICE TR CO, E81B(12), 1998, pp. 2351-2356
Citations number
16
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEICE TRANSACTIONS ON COMMUNICATIONS
ISSN journal
09168516 → ACNP
Volume
E81B
Issue
12
Year of publication
1998
Pages
2351 - 2356
Database
ISI
SICI code
0916-8516(199812)E81B:12<2351:AVADFD>2.0.ZU;2-G
Abstract
In this paper, a transceiver VLSI architecture is proposed for high speed d igital CATV modems, which can perform both the QAM and the VSB transmission s [1], [2]. The proposed architecture of all-digital dual-mode QAM/VSB rece iver consists of digital AGC, digital demodulator, fractionally spaced blin d equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture c an achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are +/-6 kHz of carrier frequ ency offset, +/- 110 ppm of symbol rate offset, and -82 dBc carrier phase-j itter at 10 kHz away from the nominal carrier frequency.