Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

In many embedded systems, a significant amount of power is consumed for off -chip driving because off-chip capacitances are much larger than on-chip ca pacitances. This paper proposes instruction scheduling techniques to reduce power consumed for off-chip driving. The techniques minimize the switching activity of a data bus between an on-chip cache and a main memory when ins truction cache misses occur. The scheduling problem is formulated and two s cheduling algorithms are presented. Experimental results demonstrate the ef fectiveness and the efficiency of the proposed algorithms.