A test methodology for core-based system LSls

Citation
M. Sugihara et al., A test methodology for core-based system LSls, IEICE T FUN, E81A(12), 1998, pp. 2640-2645
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E81A
Issue
12
Year of publication
1998
Pages
2640 - 2645
Database
ISI
SICI code
0916-8508(199812)E81A:12<2640:ATMFCS>2.0.ZU;2-2
Abstract
In this paper, we propose a test methodology for core-based system LSIs. Ou r test methodology aims to decrease testing time for core-based system LSIs . In our method, every core is supplied with several sets of test vectors. Every set of test vectors guarantees sufficient fault coverage. Each set of test vectors consists of two parts. One is based on built-in self-test (BI ST) and the other is based on external testing. These sets of test vectors are designed to have different ratio of BIST to external testing each other for every core. We can minimize testing time for core-based system LSIs by selecting from the given sets of test vectors for each core. The main cont ributions of this paper are summarized as follows. (i). BIST is efficiently combined with external testing to relax the limita tion of the external primary inputs and outputs. (ii). External testing for one of cores and BISTs for the others are perfor med in parallel to reduce the total testing time. (iii). The testing time minimization problem for core-based system LSIs is formulated as a combinatorial optimization problem to select the optimal se t of test vectors from given sets of test vectors for each core.