High-level controllability and observability analysis for test synthesis

In this study, we present a high-level testability analysis technique that evaluates the testability of a design based on the proposed controllability and observability measures. The control-data flow graph (CDFG) constructed from the VHDL description of a design is first analyzed to identify hard-t o-control conditional branches and hard-to-control/observe register transfe r statements. After the hard-to-test areas of the design are identified, th e proposed testability enhancement methods can be applied to improve the te stability of the circuit. Unlike many recent studies in the area of high-le vel test synthesis (HLTS) that focus on improving the testability of data p aths, our approach also improves the testability of synthesized circuits by enhancing the controllability of the control flow. Experimental results on several high-level synthesis benchmarks show that when this approach is us ed prior to logic synthesis, the test generation complexities are reduced w hile better fault coverage and ATPG efficiency are often achieved. Implemen tation of this technique requires minimal logic and performance overheads a nd allows test vectors to be applied at clock-speed.