RTL test justification and propagation analysis for modular designs

Modular decomposition and functional abstraction are commonly employed to a ccommodate the growing size and complexity of modern designs. In the test d omain, a divide-and-conquer type of approach is utilized, wherein test is l ocally generated for each module and consequently translated to global desi gn test. We present an RTL analysis methodology that identifies the test ju stification and propagation bottlenecks, facilitating a judicious DFT inser tion process. We introduce two mechanisms for capturing, without reasoning on the complete functional space, data and control module behavior related to test translation. A traversal algorithm that identifies the test transla tion bottlenecks in the design is described. The algorithm is capable of ha ndling cyclic behavior, reconvergence and variable bit-widths in an efficie nt manner. We demonstrate our scheme on representative examples, unveiling its potential of accurately identifying and consequently minimizing the rep orted controllability and observability bottlenecks of large, modular desig ns.