Synthesis of native mode self-test programs

Recent studies show that at-speed functional tests are better for finding r ealistic defects than tests executed at lower speeds. This advantage has le d to growing interest in design for at-speed tests. In addition, time-to-ma rket requirements dictate development of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self -test programs for microprocessors. Based on information about the instruct ion set, this high-level test generation methodology can generate instructi on sequences that exercise all the functional capabilities of complex proce ssors. Modern processors have large memory modules, register files and powe rful ALUs with comprehensive operations, which can be used to generate and control built-in tests and to evaluate the response of the tests. Our metho d exploits the functional units to compress and check the test response at chip internal speeds. No hardware test pattern generators or signature anal yzers are needed, and the method reduces area overhead and performance impa ct as compared to current BIST techniques. A novel test instruction inserti on technique is introduced to activate the control/status inputs and intern al modules related to them. The new methodology has been applied to an exam ple processor much more complex than any benchmark circuit used in academia today. The results show that our approach is very effective in achieving h igh fault coverage and automation in at-speed self-test generation for micr oprocessor-like circuits.