Versatile BIST: An integrated approach to on-line/off-line BIST for data-dominated architectures

Built-in Self Test (BIST) is increasingly being used in production testing of VLSICs. In BIST, extra logic is implemented to generate test patterns an d compact test responses on chip. However, this extra logic is used only du ring the test mode. Traditionally, BIST structures used for on-line testing have been different from the BIST structures used for off-line production testing. Replicated hardware, comparators and checkers are typical on-line BIST structures. This is because on-line BIST techniques are mostly based o n space or time or information redundancy. On the other hand, typical off-l ine BIST structures include linear feedback shift register (LFSR) based pat tern generators and multiple input signature register (MISR) based test res ponse compactors. In this paper we report a Versatile BIST approach (VBIST) that targets both off-line and on-line self test. VBIST uses off-line BIST circuitry for on- line testing as well. Unlike traditional on-line self test approaches, VBIS T does not use functional data as test inputs. Rather, VBIST generates test patterns and compacts test responses during the normal mode of operation. Furthermore, VBIST coordinates this generation and application of test patt erns and compaction of test responses with the usage profile of the modules in the design. VBIST entails little additional impact on performance and a rea of the design (vis-a-vis the performance and area of a design with off- line BIST). We validated the proposed approach using the Synopsys Behaviora l Compiler as the synthesis framework and by writing synthesis scripts for incorporating VBIST constraints.