Unique ESD failure mechanisms during negative to Vcc HBM tests

HEM ESD tests on two types of 0.6 mu m DRAM devices showed that internal ci rcuit or output driver failures would occur after the input or I/O pins wer e ESD stressed negative with respect to Vee at ground. These failures occur red at lower than expected ESD stress voltages due to power-up circuit inte ractions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin's ESD protection circui t. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vee bond pad can result in low voltage ESD failures. (C) 1998 Elsevier Science Ltd. All rights reserved.