J. Ranaweera et al., Simulation, fabrication and characterization of a 3.3 V flash ZE(2)PROM array implemented in a 0.8 mu m CMOS process, SOL ST ELEC, 43(2), 1999, pp. 263-273
This paper describes a Zener based Rash memory cell (ZE(2)PROM), programmed
from hot electrons generated by a heavily doped reverse biased p(+)n(+) ju
nction attached to the drain. The cell can be implemented in a NOR type mem
ory array. It uses an orthogonal write technique to achieve fast programmin
g with low power dissipation and reduced drain disturbance. The modeling of
the charge transfer behavior of the Rash ZE(2)PROM cell is also done to de
scribe the charging and discharging of the floating gate during programming
and erasing. The flash ZE(2)PROM arrays were implemented in a 0.8 mu m lit
hography CMOS process flow in which the n-LDD step was replaced with a one
sided p(+) boron implant with a doping level of similar to 10(19) cm(-3). T
his minor change to a standard CMOS process, makes the concept highly attra
ctive for embedded memory applications. A programming time of 850 ns at 3.3
V supply was achieved on fabricated lest devices. (C) 1998 Elsevier Scienc
e Ltd. All rights reserved.