Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

A novel dynamic-floating-gate technique is proposed to improve ESD robustne ss of the CMOS output buffers with small driving/sinking currents. This dyn amic-floating-gate design can effectively solve the ESD protection issue wh ich is due to the different circuit connections on the output devices. By a dding suitable time delay to dynamically float the gates of the output NMOS /PMOS devices which are originally unused in the output buffer, the human-b ody-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater tha n 8 kV (1500 V) in a 0.35-mu m bulk CMOS process. (C) 1998 Elsevier Science Ltd. All rights reserved.