Deposition and etch processes: continuum film evolution in microelectronics

Aspects of modeling and simulation of topography evolution during depositio n and etch processes used in the fabrication of integrated circuits are dis cussed. Overall, we hope to demonstrate that combined simulation and experi mental studies of film profiles and composition profiles inside features is a valuable tool in efforts to arrive at useful kinetic and transport model s. In particular, conformality limitations and film composition variations inside features for films deposited at low pressures are explained using ex amples of studies that combine transport and reaction simulations of deposi tion processes and carefully designed experimental work. The technical pres entation is divided into three major parts. In the first section, we demons trate that thermal systems can be modeled without "calibrating" the transpo rt and reaction models used, though calibration can still be useful. The pr ocess considered in this section is the thermal deposition of SiO2 from TEO S (tetraethoxysilane). We discuss the use of film profile information to de cide between two kinetic models for the deposition process, then we discuss one way to integrate reactor scale and feature scale models in order to ca pture "microloading" due to changes in local pattern density. The second se ction demonstrates the state of topography simulation for plasma processes. We demonstrate the use of physically motivated models that in general requ ire calibration from experimental data for a given set of operating conditi ons. As our first plasma example, we use the sputter deposition of Ti-W to demonstrate the existence of composition profiles inside features. We then use etch simulations to show how simulations can be used to test proposed c hemical and/or physical phenomena. The last major section is a case study o n plasma enhanced deposition of SiO2 from TEOS and oxygen (PETEOS) that dem onstrates the roles of "3d/2d" and "3d/3d" (transport dimensionality/surfac e dimensionality) topography simulators in "virtual wafer fabs", The same m ethodology would apply to most topography relevant processes, including thi n film flow processes. (C) 1998 Elsevier Science B.V. All rights reserved.