Gate overlap length reduction and shallow junction formation in high-performance fine MOSFETs by ion implantation through thin oxide film

A gate overlap length of only 16 nm between the gate and the source/drain h as been achieved in fine n-type metal oxide semiconductor field effect tran sistors with 0.1 mu m gate length by arsenic ion implantation through a thi n oxide film formed by chemical vapour deposition. The presented technique enables the gate overlap length to be reduced by less than half of the valu e for conventional lower energy implantation while maintaining a shallow ju nction depth for the source/drain.