High performance 0.04 mu m PMOSFET

Citation
K. Goto et al., High performance 0.04 mu m PMOSFET, FUJITSU SCI, 34(2), 1998, pp. 135-141
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
FUJITSU SCIENTIFIC & TECHNICAL JOURNAL
ISSN journal
00162523 → ACNP
Volume
34
Issue
2
Year of publication
1998
Pages
135 - 141
Database
ISI
SICI code
0016-2523(1998)34:2<135:HP0MMP>2.0.ZU;2-D
Abstract
This paper describes a high-performance 0.04-mu m PMOSFET with a 7-nm-deep ultrashallow junction. An ultra-low energy implantation of B10H14+ at 2 keV (with effective boron energy of 0.2 keV), which does not cause transient-e nhanced diffusion, is employed for extension formation. To prevent thermal diffusion, we developed a two-step activation annealing process (2-step AAP ) that forms a shallow extension with low-temperature annealing after deep source and drain formation. A maximum drive current of 0.40 mA/mu m (@ I-of f of 1 nA/mu m and V-d = -1.8 V) was achieved, and the smallest PMOSFET (wi th a L-eff of 0.038 mu m) has been demonstrated for the first time. We also achieved a low S/D series resistance R-sd Of 760 Ohm-mu m, even when high sheet resistance (>20 k Ohm/sq) is applied to the extension regions.