Techniques for minimizing power dissipation in scan and combinational circuits during test application

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using builtin self-test (BIST ), The problems are shown to be intractable, Heuristics to solve these prob lems are discussed. We show that heuristics with good performance bounds ca n be derived for combinational circuits tested using BIST, Experimental res ults show that considerable reduction in power dissipation can be obtained using the proposed techniques.