Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) al gorithm has enabled the design of pipelined architectures for real-time tra nsversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorith m, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS archit ecture with minimal adaptation delay for any given sampling rate. The archi tecture is synthesized by using a number of function preserving transformat ions on the signal flow graph representation of the DLMS algorithm. With th e use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 mul tiplexer. In the second part of this paper, we extend the synthesis methodo logy described in the first part, to synthesize pipelined DLMS architecture s whose power dissipation meets a specified budget. This low-power architec ture exploits the parallelism in the DLMS algorithm to meet the required co mputational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.