The impact of rate control algorithms on system-level VLSI design

This paper presents an evaluation of rate control algorithms from a system- level VLSI design viewpoint. Rate control in video coding has a significant influence on the coded bit rate and image quality. Many rate control algor ithms have been proposed mainly focusing on the optimal rate-distortion per formance without considering their performance on the VLS implementation. T he purpose of this study is not to propose a hardware architecture for any specific algorithm but to study the algorithm impact on hardware design. Ba sed on our finding, a system designer should choose an algorithm not only g ood in rate control performance but also good in hardware implementation. W hen implementing and comparing a few rate control algorithms using a generi c processor structure, we found that, in addition to the ordinary computati onal complexity, the internal buffer size is also very critical in VLSI rea lization. Several picture sequences have been tested including one sequence constructed specifically to simulate a difficult case for rate control. In this paper, three different types of popular rate control algorithms have been analyzed based on their picture quality, the internal buffer size, and the hardware cost. The methodology and results presented here provide usef ul guidelines for selecting an appropriate rate control algorithm for syste m-level VLSI designers.