Architecture of a memory manager for an MPEG-2 video decoding circuit

A study of the MPEG-2 video decoding standard in Main Profile @ Main Level has been performed, comparing the different solutions existing for the VLSI implementation of the basic functions (Huffman decoding, IDCT...) included in the standard. Afterwards, a new dynamically configurable architecture i s proposed for the memory manager, which is necessary to deal with the larg e data flow inside the decoder. It is aimed at interfacing the external mem ory, arbitrating the access requests coming from the different decoding uni ts and allowing generic memory requests through the definition of virtual a ddresses. It is shown that, by means of a particular data organization, the circuit requires an external memory, which is a 2-MB DRAM in fast page or EDO mode, accessible via a 64-bit bus. The memory manager works at 27 MHz a nd allows a real-time decoding for MP @ ML bitstreams. It has been synthesi zed in a 0.8-mu m two-metal CMOS technology and presents a total area of 5. 4 mm(2) for 6500 gates.