Sf. Hsiao et Jy. Chen, Design, implementation and analysis of a new redundant CORDIC processor with constant scaling factor and regular structure, J VLSI S P, 20(3), 1998, pp. 267-278
Citations number
23
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
A new high-speed redundant CORDIC processor is designed and implemented bas
ed on the double rotation method, which turns out to be the two-dimensional
(2D) Householder CORDIC, a special case of the generalized Householder COR
DIC in the 2D Euclidean Vector space. The new processor has the advantages
of regular structure and high throughput rate. The pipelined structure with
radix-2 signed-digit (SD) redundant arithmetic is adopted to reduce the ca
rry-propagation delay of the adders while the digit-serial structure allevi
ates the burden of the hardware cost and I/O requirement. Compared to previ
ously proposed designs, the new CORDIC processor preserves the constant sca
ling factor, an important merit of the original CORDIC, and thus does not r
equire any complicated division or square-root operations for variable scal
ing factor calculation. Furthermore, the processor is well suited to VLSI i
mplementation since it does not call for any irregularly inserted correctin
g iterations. Both angle calculation mode for computing trigonometric funct
ion and vector rotation mode for plane rotations are supported. Practical V
LSI chip implementation of the fixed-point redundant CORDIC processor using
0.6 mu m standard cell library is given including detailed numerical error
analysis.