The effects of process induced gate-to-source/drain junction separation inMOSFET structures

As device size decreases, the effect of process fluctuations on the device structure and performance will become more apparent. Implantation, annealin g and etching fluctuations can lead to a separation between the edge of the gate and the source/drain extensions. This paper investigates the effect o f separation on the device characteristics of 1.5 mu m mask gate length MOS FETs. It was found that introducing separation reduced the overall peak sub strate current, increased the breakdown voltage, increased the hot carrier hardness and greatly increased the device's lifetime. However, separation a lso increased the threshold voltage and reduced the drain current. The sepa ration was found not to contribute any extra parasitic resistance but manif ested itself as an increase in the effective electrical channel length. Var ying the amount of separation demonstrated that the input capacitance was r educed, and that the speed was increased relative to a standard LDD MOSFET. (C) 1998 Elsevier Science Ltd. All rights reserved.