A FAST MODULAR EXPONENTIATION FOR RSA ON SYSTOLIC ARRAYS

This paper presents two systolic algorithms for modular exponentiation s based on a k-SR representation. In a systolic k-SR scheme, throughpu t is one modular exponentiation of a message block having n digits in every clock cycle, with a latency of nearly 5n/4 cycles to output the final result. The speedup for a group of messages having l message blo cks is around (5/6l + 2/3n), compared to a single processor or process ing element for modular multiplications. The scheme saves nearly n/4 p rocessing elements and around n/4 modular multiplications, compared wi th the scheme in [23].