TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS

Citation
P. Girard et al., TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS, Electronics Letters, 33(6), 1997, pp. 485-486
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
ISSN journal
00135194
Volume
33
Issue
6
Year of publication
1997
Pages
485 - 486
Database
ISI
SICI code
0013-5194(1997)33:6<485:TFRPIC>2.0.ZU;2-2
Abstract
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. A post-mapping technique is proposed that can reduce the power dissip ation by performing gate resizing. Experiments performed on benchmark circuits have shown a power reduction in the range from 4.2 to 27.9% c ompared to circuits without resizing, with solutions obtained in a sho rt computation time (no more than 8.5s).