With the advent of portable and high density microelectronic devices,
the power dissipation of VLSI circuits is becoming a critical concern.
A post-mapping technique is proposed that can reduce the power dissip
ation by performing gate resizing. Experiments performed on benchmark
circuits have shown a power reduction in the range from 4.2 to 27.9% c
ompared to circuits without resizing, with solutions obtained in a sho
rt computation time (no more than 8.5s).