A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

A regenerator-section terminating digital large-scale-integration chip for an STM-16 (2,5-Gbit/s synchronous optical network/synchronous digital hiera rchy) regenerator has been developed using low-power bipolar technologies. The high-speed performance of bipolar devices enabled four or more chips, i ncluding a demultiplexer and a multiplexer. to be integrated into a single chip, The low-power dissipation of 557 mW, only about one-tenth that of pre viously reported chips, was achieved through the use of four design steps: one-chip integration architecture, power management, 2.5-V emitter-coupled logic, and power optimization.