A new true-single-phase-clocking BiCMOS dynamic pipelined logic family forhigh-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic c ircuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynam ic pipelined system applications are proposed and analyzed, In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-ful l-swing operation. The circuit performance of the proposed new dynamic logi c circuits and dynamic latch logic circuits in both domino and pipelined ap plications are simulated by using HSPICE with 1-mu m BiCMOS technology, Sim ulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and p ower dissipation/MHz of the pipelined system, which is constructed by the n ew clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-eva luate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked RIGS transistors, are about 2.36 (2.2) times and 1.15 (1.1) ti mes those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V , respectively, Moreover, the chip area of these two BiCMOS pipelined syste ms is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1-mu m BiCMO S technology verifies the speed advantage of the new BiNMOS dynamic logic c ircuit, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, Low-voltage dynamic pipelined system applications.