The motivation of designing asynchronous memory arises from the recent deve
lopment of asynchronous processors. As different from the conventional desi
gn, the proposed asynchronous static RAM can 1) communicate with other asyn
chronous systems based on a four-phase handshaking control protocol and 2)
generate the read/write completion signals with increased average speed by
the variable bit-line load concept. The techniques investigated include 1)
dual-rail voltage sensing completion detection for read operation and 2) mu
ltiple delays completion generation for write operation, In this paper, the
performances of these techniques are evaluated for 1-Mb memory with four r
egions of bit-line segmentation. The simulated and measured results are pre
sented and compared.