Interconnect simulation in a fast timing simulator ILLIADS-I

This paper presents a new technique to simulate RLC/RC interconnects and dr iving nonlinear circuits with high computational efficiency. We introduce I LLIADS-I, a fast transistor-level timing simulator for MOS circuits driving RLC/RC interconnects. The RLC/RC interconnect networks are reduced to an a ppropriate model and then simulated in the timing simulator as a modified g eneric circuit primitive. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms, Experimental r esults show ILLIADS-I is both accurate and fast. The speed advantage is sho wn to increase with the circuit size for multilevel interconnect networks w ith nonlinear driver and load circuits.