Constraint analysis for DSP code generation

Code generation methods for digital signal-processing (DSP) applications ar e hampered by the combination of tight timing constraints imposed by the pe rformance requirements of DSP algorithms and resource constraints imposed b y a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis o f the combination of resource and timing constraints. The analysis identifi es implicit sequencing relations between operations in addition to the prec eding constraints. Without the explicit modeling of these sequencing constr aints, a scheduler is often not capable of finding a solution that satisfie s the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low reg ister requirements.