Miniaturization of space electronics with chip-on-board technology

Miniaturization of space electronics by eliminating individual chip package s is attractive not only because of the advantage of reduction in both volu me and weight but also because of the potential improvement in reliability associated with elimination of the first level of packaging at the chip. Mo st importantly, miniaturization can lead to significant cost saving in a sp ace program since a smaller launch vehicle may be used. The APL study of ch ip-on-board technology began with the miniaturization of a magnetometer sig nal processor to verify the manufacturability of the new advanced packaging process. Subsequently, encapsulant-covered dynamic-random-access-memory te st boards and triple-track chips were subjected to an environmental stress program to qualify the technology for flight. This article presents an over view of the chip-on-board technology: the approach, methodology, and test r esults and its significance and potential effect on the future direction of space programs.