Impact of processing parameters on leakage current and defect behavior of n(+)p silicon junction diodes

In this study the origin of the leakage current of n(+)p diodes and the imp act of process conditions on the leakage current is investigated. The influ ence of isolation modules, namely, conventional local oxidation of silicon (LOCOS) vs. polybuffered LOGOS, and different junction annealing conditions , namely, furnace anneal and rapid thermal anneal, on the diode leakage cur rent is discussed. The diode leakage current level distribution over a wafe r is very sensitive to specific processing steps, such as active area defin ition. For large peripheral diodes in p-type substrate or in p-well, the le akage current strongly depends on junction annealing conditions. The diodes processed with furnace anneal have one order of magnitude lower leakage cu rrents compared to the diodes with rapid thermal anneal. This difference in leakage current is due to different surface generation velocities at the s ilicon-oxide isolation interface. (C) 1999 The Electrochemical Society. S00 13-4651(98)02-067-9. All rights reserved.