We present a 128-channel prototype chip for the binary readout of silicon s
trip detectors which has been designed and manufactured in the radiation ha
rd DMILL technology. The goal of this development was to demonstrate the fe
asibility of building in the DMILL technology, a radiation hard chip suitab
le for the binary readout architecture for the ATLAS SCT. A single chip com
prises the front-end circuitry, the binary pipeline and the back end readou
t circuitry. The architecture as well as the designs of the individual bloc
ks are discussed in the paper. Measurements confirm that full functionality
of all blocks of the chip have been achieved at a clock frequency of 40 MH
z, meeting the design specification. (C) 1999 Elsevier Science B.V. All rig
hts reserved.