ELECTRICAL CHARACTERIZATION OF FLUORINE-IMPLANTED GATE OXIDE STRUCTURES

In the ongoing quest for thinner and more reliable gate dielectrics fo r microelectronics, fluorination of gate oxide structures has emerged as a leading technique. In this work, the fluorine is implanted into t he polysilicon gate before the poly etch. After the subsequent poly et ch and anneal, the samples are not sent through the remainder of the p rocess, but are subjected to electrical reliability stressing by two m ethods: constant-current Fowler-Nordheim tunnelling stress, and consta nt-voltage stress (J-t analysis). Two different fluorination cases (do ses and implant energies) are studied, along with unimplanted controls . In the fluorinated cases, improvement vs. controls is found in devic e reliability indicators: mid-gap D-it, Q(f) and Delta V-th. J-t analy sis corroborates the improvement, and the combination of techniques is found to offer a more comprehensive view of complex variations in flu orinated oxide properties.