An improved drain-current-conductance method with substrate back-biasing

Authors
Tan, CB Chim, WK Chan, DSH Lou, CL
Citation
Cb. Tan et al., An improved drain-current-conductance method with substrate back-biasing, IEEE DEVICE, 46(2), 1999, pp. 431-433
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
46
Issue
2
Year of publication
1999
Pages
431 - 433
Database
ISI
SICI code
0018-9383(199902)46:2<431:AIDMWS>2.0.ZU;2-R
Abstract
A previously developed drain-current-conductance method (DCCM) is extended to investigate the effect of back-bias on LATID NMOSFET's. For the same eff ective gate overdrive, the extracted drain and source series resistances in crease as the back-bias is increased. Two-dimensional device simulation sho wed that the increased back-bias results in reduced current contour values at the drain/source regions as a result of the increase in the series resis tances.