In this paper we present the design of a new high-speed multiplication unit
. The design is based on non-overlapped scanning of 3-bit fields of the mul
tiplier. In this technique the partial products of the multiplicand and thr
ee bits of the multiplier are pre-calculated using only hardwired shifts. T
hese partial products are then added using a tree of carry-save-adders, and
finally the sum and carry vectors are added using a carry-lookahead adder.
In the case of 2's complement multiplication the tree of carry-save-adders
also receives a correction output produced in parallel with the partial pr
oducts. The algorithm is modelled in a hardware description language and it
s VLSI chip implemented. The performance of the new design is compared with
that of other recent ones proposed in literature.