Scalability of gate/N- overlapped lightly doped drain in deep-submicrometer regime

In this paper an experimental study of the scalability of a gate/N- overlap ped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 mu m. The allowable power supply voltage is obtained by investigat ing the time-dependent dielectric breakdown reliability, the minimum operat ing voltage, the gate-induced-drain-leakage current, the drain-induced-barr ier-lowering effect and the DC hot carrier reliability. It was found that t he maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a sin gle drain (SD) structure when V-Dmax is applied as a supply voltage. The OL -LDD structure has a smaller C-GD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with sma ller L-G. Consequently, the performance of complementary metal-oxide-semico nductor (CMOS) devices with the OL-LDD structure is superior to that with t he SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 mu m CMOS devices.