Implementation of a sliding memory plane image processor

This paper presents architectures and implementation of a Sliding Memory Pl ane (SliM) Image Processor to build a SIMD parallel computer. The paper als o proposes an enhanced multiplication algorithm to reduce the gate count an d the number of cycles. The SliM chip consists of mesh-connected 5 x 5 PEs. Due to the idea of sliding, that is, overlapping the inter-PE communicatio n time with the computation time, SliM can greatly reduce the inter-PE comm unication overhead. In addition, four operations corresponding to ALU, shif t, delta I/O, and inter-PE communication can be grouped into an instruction to be executed in a cycle simultaneously. The implemented SliM chip operat es at 25 MHz and gives 625 MIPS. Because of a mesh topology, a large number of chips can be easily connected to form a SIMD parallel computer. We have implemented the scalable SliM Array Processor and developed parallel algor ithms for real-time image processing. (C) 1999 Academic Press.