Two FIFO ring performance experiments

Asynchronous circuits are often perceived to operate slower than equivalent clocked circuits. We demonstrate with fabricated chips that asynchronous c ircuits can be every bit as fast as clocked circuits. We describe two high- speed first-in-first-out (FIFO) circuits that we used to compare the perfor mance of asynchronous FIFO's with that of conventionally clocked shift regi sters. The first FIFO circuit uses a pulse-like protocol, which we call the Asynchronous Symmetric Persistent Pulse Protocol (asP*), to advance data a long a pipeline of conventional latches. Use of this protocol requires care ful management of circuit delays. The second FIFO circuit uses a transition signaling protocol and special transition latches to store data. These tra nsition latches are fast, but they are about 50% larger than conventional l atches. Measurements obtained from chips fabricated in 0.6-mu m CMOS and fr om SPICE simulations show that the throughput of the first FIFO design matc hes that of a conventionally clocked shift register design, with a maximum throughput of 1.1 Giga data items per second The throughput of the second d esign exceeds the performance of the asP* design and achieves a maximum thr oughput of 1.7 Giga data items per second. We have extensively tested the c hips and have found them to operate reliably over a very wide range of cond itions.