Logic decomposition of speed-independent circuits

Logic decomposition is a well-known problem in logic synthesis, but it pose s new challenges when targeted to speed-independent circuits. The decomposi tion of a gate into smaller gates must preserve not only the functional cor rectness of a circuit but also speed independence, i.e., hazard freedom und er unbounded gate delays. This paper presents a new method for logic decomp osition of speed-independent circuits that solves the problem in two major steps: 1) logic decomposition of complex gates and 2) insertion of new sign als that preserve hazard freedom. The method is shown to be more general th an previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks.