Defect-oriented testability for asynchronous IC's

For a CMOS manufacturing process, asynchronous IC's are similar to synchron ous IC's. The defect density distributions are similar, and hence, so are t he fault models and fault-detection methods. So, what makes Its think that asynchronous circuits are much harder to test than synchronous circuits? Be cause the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? That may very well be a tempo ral hurdle. Many test methods have already been reevaluated and successfull y adapted from the synchronous to the asynchronous test domain. The paper a ddresses one of the final hurdles: I-DDQ testing. This type of test method, based on measuring the quiescent power supply current, is very effective f or detecting (resistive) bridging faults in CMOS circuits. Detection of bri dging faults is crucial, because they model the majority of today's manufac turing defects. I-DDQ fault effects ave sensitized in a particular stare or set of states and can only be detected if we stop the circuit operation ri ght there. This is a problem for asynchronous circuits, because their opera tion is self timed. In the paper we quantify the impact of self timing on the effectiveness of I-DDQ-based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do t he same for logic voltage testing and stuck-at faults. The approach is illu strated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general .