The vertical heterojunction MOSFET

In this paper a new vertical MOS transistor structure including its fabrica tion and electrical results will be presented. It overcomes the technologic al and physical limitations encountered when scaling the classical planar t ransistor into the deep submicron regime. It solves the technological issue by defining the channel length through epitaxial growth instead of lithogr aphy. The physical phenomenon of drain induced barrier lowering (DIBL) is l argely decreased through the use of a heterojunction between source and dra in. (C) 1998 Elsevier Science S.A. All rights reserved.