Selectively grown vertical Si MOS transistor with reduced overlap capacitances

Vertical p-MOS transistors with channel length of 130 nm have been fabricat ed using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths a nd high integration densities while still using optical lithography to defi ne lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for h igh speed applications. The use of SEG instead of blanket epitaxy avoids th e deterioration of the Si-SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First nan-optimized p-channe l MOSFETs With a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f(T) = 2.3 GHz and f(ma x) = 1.1 GHz. (C) 1998 Elsevier Science S.A. All rights reserved.