Comparison of lateral and vertical Si-MOSFETs with ultra short channels

The fabrication of a vertical MOSFET is compatible with standard CMOS techn ology for lateral MOSFETs. Process modules like gate oxidation, polysilicon gate contact, oxide spacer, contact implantation, salizidation, isolation and metallization were used for the integration of lateral and vertical het ero- and homo-MOS devices. For the vertical device the epitaxy of the drain -channel-source layer stack and the mesa etching are new processes. For a 1 00 nm vertical n-MOSFET (N-A = 1 x 10(18) cm(-3)) with a 5 nm thick thermal oxide we obtained: g(m) = 375 mS/mm (U-DS = 2 V), U-T = 0.3 V, S = 80 mV/d ec and 1(DMIN) = 1 x 10(-10) A/mu m. For comparison, with a 0.5 pm lateral n-MOSFET we achieved: g(m) = 340 mS/mm, U-T = 0.34 V, S = 66 mV/dec and I-D MIN = 1 x 10(-10) A/mu m. In addition, the intrinsic RF performance has bee n simulated to complete the comparison of the lateral and vertical n-MOSFET . It is shown, that the high source-drain capacitance CDS Of the vertical M OSFET reduces the transit frequency. (C) 1998 Elsevier Science S.A. All rig hts reserved.