Effect of express lots on production dispatching rule scheduling and cost in VLSI manufacturing final test process

We evaluate the effect of express lots on production dispatching rule sched uling and cost in VLSI manufacturing final test process. In the assignment of express lots, we make comparisons of two rules, First In First Out (FIFO ) rule which is widely used and WEIGHT+RPM rule which considers the time re quired for jig and temperature exchanges, the remaining processing time of the machine in use and the lot waiting time in queue. When using FIFO rule, the test efficiency begins to deteriorate and the test cost per chip begin s to increase, if the content of express lots exceeds 15%. Furthermore, for 30% of express lots' content, the number of total processed lots decreases by 19% and the test cost per chip increases by 22% in comparison to the ca ses including no express lots. For WEIGHT+RPM rule, however, the test effic iency does not deteriorate and the test cost per chip does not increase eve n if the content of express lots is increased up to 50%. When we use WEIGHT +RPM rule, Express Lots Tolerances (ELTs), defined as the maximum content o f express lots which permits the deterioration of the system characteristic s by 5%, are about three times as high as ones when using FIFO rule. It is also found that WEIGHT+RPM rule maintains higher ELTs against the changes i n the numbers of planned chips and prepared jigs as compared with FIFO rule .