Megabit-class size-configurable 250-MHz SRAM macrocells with a squashed-memory-cell architecture

High-speed and low-power techniques are described for megabit-class size-co nfigurable CMOS SRAM macrocells. To shorten the design turn-around-time, th e methodology of abutting nine kinds of leaf cells is employed; two-level v ia-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-c ell architecture using drench isolation and stacked-via-holes is proposed t o reduce access times and power dissipation. To shorten the time for writin g data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-typ e two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop , current paths are separated so as not to cause common impedance. To confi rm the techniques described in this paper, a 1-Mb SRAM test chip was fabric ated with an advanced 0.35-mu m CMOS/bulk process. The SRAM has demonstrate d 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power d issipation was obtained at a practical operating frequency of 150-MHz.