A floating-point divider using redundant binary circuits and an asynchronous clock scheme

This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme redu ce the delay time and area penalty. The redundant binary representation of +1 =(1, 0), 0 =(0, 0), -1 =(0,1) is applied to the all mantissa division ci rcuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit fo r the asynchronous clock scheme eliminates clock margin overhead. The gener ator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operati on by the asynchronous scheme and the modified redundant-binary addition/su btraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies ope rates at 42.1 ns with 0.35 mu m CMOS technology and triple metal interconne ctions. The small core of 13.5 k transistors is laid-out in a 730 mu m x 91 0 mu m area.