The integrated scheduling and allocation of high-level test synthesis

This paper presents a high-level test synthesis algorithm for operation sch eduling and data path allocation. Data path allocation is achieved by a con trollability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other ha nd, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the sc heduling and allocation tasks are performed independently, our approach int egrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop a nalysis is performed at register-transfer level in order to avoid loop crea tion during the integrated test synthesis process. With a variety of synthe sis benchmarks, experimental results show clearly the advantages of the pro posed algorithm.