Estimation of BIST resources during high-level synthesis

Lower bound estimations of functional resources at various stages of high-l evel synthesis have been developed to guide synthesis algorithms toward opt imal solutions. In this paper we present lower bounds on the number of rest resources (i.e., registers that generate pseudo-random test patterns and/o r compress test responses) required to test a synthesized data path using b uilt-in self-test (BIST). The bounds on different types of test resources a re proved to be individually achievable and experiments show that in most c ases the bounds can be achieved simultaneously and with minimum number of f unctional registers. Efficient ways of computing the lower bounds are devel oped. The estimations are performed on scheduled data flow graphs with a gi ven module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.